Power Reduction Techniques in ASIC Design

PDN Concepts | 01 December 2018

When it comes to reducing power dissipation in a chip, there are different techniques followed in industry at different levels of abstraction (circuit-level, logic-level, physical-level etc.,). In this blog post, we will focus on physical-level power management techniques and industry jargons related to power management in chip design.

Before proceeding with this tutorial, kindly read Power Distribution Network in ASIC Physical Design so that you get to know some of the basic concepts needed to understand the concepts that we will discuss in this tutorial.


After reading this tutorial, we will understand

  • What are power domains?
  • What are voltage islands?
  • What are power management cells?
  • What is a power management unit?
  • What are ESD cells?
  • What are some of the advanced low power techniques?

Power Domains

Imagine we have four IPs (blocks or hard-macros) of different functionality in a chip. Let’s say IP1 is a CPU, IP2 is a Graphic Processor, IP3 is an Audio Processor and IP4 is a Power Management Unit (mixed signal). Based on its functionality, we can say that

  • IP1 is a timing-critical block and operates at highest frequency as it’s the CPU. Let’s say it operates at 1.2V.
  • IP2 and IP3 are switchable blocks i.e. we can switch off power to these blocks to save some power. Let’s assume these two operates at 1.5V.
  • IP4 is an always ON block that needs to be ON all the time as it manages the power supply. Let’s say it operates at 3.1V.
Figure 1. Power Domains (Multi-voltage design)

A power domain is a logical (virtual) portion of the design in which the logic cells in that power domain share common power supply characteristics. Each hierarchical cell in the design can belong to only one power domain.

Defining power domains on logical hierarchical boundaries is the ideal and preferred approach instead of defining power domains for logical hierarchies that are different.

In our case, IP1 belongs to PD1 (or Power Domain 1), IP2 belongs to PD2, IP3 belongs to PD3 and IP4 belongs to PD4 (each power domain shown in different colors in Figure 1).

Also note that, a power domain is purely logical and not physical. To realize power domains physically, we define voltage islands or voltage areas in the physical layout.

Voltage Islands

Voltage island is a physical realization of a power domain in a design. In our case, all the different IPs will have their dedicated rectilinear coordinates that defines the island boundaries, power mesh structure and switching characteristics of each power domain, respectively (as shown in Figure 1). Power mesh and switching characteristics for IP1 can be different than other IPs and vice-versa.

Logic cells that talk within their own power domain has no power constraint. But cells that have signals that communicate from one power domain to another, say IP1 to IP3 requires special power management cells such as isolation cells and level shifters.

Power Management Cells

To reduce power consumption and to protect interfaces between power domains, there are special types of standard cells defined in library such as isolation cells, level shifters, retention registers, power switch and always ON buffers as shown in Figure 2.

Figure 2. Power management cells to reduce power consumption

Level Shifters

If a signal from IP1 talks to IP3, we need a level shifter which shifts this signal’s voltage level from 2V to 1.5V. Level shifters are special power management cells that has two power supply nets.

  1. Input supply net - connected to the voltage supply of driver’s power domain.
  2. Output supply net - connected to the voltage supply of receiver’s power domain.

There are two types of level shifters namely buffer-type level shifters and enable level shifters. Level shifters must be checked for proper drive strength and accurate timing as signals are transitioned from one voltage level to another voltage level.

Isolation Cells

If a signal from switchable IP2 block talks to always ON IP4 block, then if IP2 is powered off, all the outputs of IP2 power domain will be in an unknown state X. Thus, we need to properly isolate these unknown output X values to protect always ON power domain IP4. Connecting a shut-down logic and active logic can also cause design issues such as spurious signal propagation and crow-bar current.

Thus, isolation cells are added to the switchable power domain IP2. These isolation cells are AND/OR gates where one input is the output of a cell in switchable domain (which might cause X propagation) and other input is a controlling value (from always ON domain) to prevent unknown state propagation to always ON domain.

Power Switches

As shrinking technology node increases leakage power, we need power switches to turn off power to CMOS transistors when they aren’t switching. When the logic in a power domain is inactive, we can turn off the power to this power domain using a power switch to save leakage power.

Power switches are added between the main supply and the virtual supply to be shutdown. The virtual supply is the power supply to standard cell supply rails.

Retention Registers

There are cases in which you wish to retain the states of sequential cells in a switchable power domain, say IP2, even when its turned off. To retain the state values of sequential elements, retention registers are used.

These registers hold the state of sequential cells in that power domain even when power is turned off. In layout, it’s viewed like randomly glowing bulbs in darkness.

One tradeoff in using retention registers is that it needs extra area as well as extra routing resources (power + signal) in the design.

Always ON buffers

When power is turned off for a switchable domain, say IP3, there might be cases where some logic needs to be active during shutdown. These logic includes control signals to retention registers or power switches as well as enable signals to isolation cells or level shifters. Sometimes it could also be signals in the feedthrough paths that travel from one power domain to another.

In these cases, always ON buffers or inverters are used which remain active during shutdown. There are two types of always ON cells such as

  1. Single rail always ON cells
  2. Dual rail always ON cells

Power Management Unit (PMU)

Multi-supply voltage techniques (using power domains) as discussed above can reduce power consumption of a chip as not all the blocks in the design needs exact power supply from a battery (most blocks are made switchable). If we have multi-supply voltage values for each power domain in our design, how does the single power supply that comes out from our battery gets transformed into different voltage levels?

The answer is Power Management Unit (PMU) or Power Management Integrated Circuit (PMIC) - [wikipedia].

A dedicated power management unit takes in single power supply from our battery and produces the necessary voltage levels needed for the design. This PMU can be a part of a chip (such as IP4) or outside the chip (a dedicated IC called PMIC) depending on packaging and cost requirements.

A typical power distribution network for a smartphone or tablet or any other gadget uses a PMU or a PMIC to convert single battery power supply into different block-level power supplies which is controlled by the operating system through I2C or any other protocol as shown in Figure 3.

Two main components in a PMIC are

  1. DC-DC converter, an electronic circuit that converts a source of Direct Current (DC) from one voltage level to another.
  2. Low Dropout Regulator, a linear DC electronic circuit that can regulate the output voltage i.e. make the output voltage steady.

Based on the functionality, DC-DC converters are further divided into

  1. Buck converters (Step-Down)
  2. Boost converters (Step-Up)
  3. Buck-Boost converters
Figure 3. Power Distribution Network in a smartphone

Advanced Low Power Techniques

Some of the commonly used advanced low power techniques to reduce power consumption in CMOS are shown in Figure 4. All the below mentioned advanced power optimization techniques require knowledge of something called as UPF or Unified Power Format which is the IEEE standard followed in industries to specify power intent of a design. We will learn about UPF in a separate blog post.

Figure 4. Advanced Low Power Techniques

1. Multi-voltage design

This technique assigns different voltages (power domains) for different regions in the design where these different voltages levels are obtained or controlled using a PMIC or PMU. The interfaces between different power domains need to be managed using level shifters and/or isolation cells. This technique reduces dynamic power.

2. Power Gating (Shutdown)

This technique uses a single voltage throughout the design with switchable regions which can be turned off to reduce power. Switching off and switching on power requires power switches which are MTCMOS cells which uses LVT during normal mode (to reduce short circuit power) and uses HVT during off mode (to reduce leakage power).

Again these power switches requires control signals from a PMIC or PMU. This technique greatly reduces leakage power as some blocks are completely switched off when their functionality is not needed.

Due to higher load in multi-million instance based design, large amount of inrush current flows to charge the internal capacitors. To reduce this inrush current, power switches are placed in a daisy chain like arrangement.

3. Multi-voltage + Power Gating (Shutdown) with State Retention

This technique combines the above two approach with state retention registers in the switchable regions of the design. This is the most commonly used approach to reduce power consumption of a chip. This techniques reduces both dynamic and leakage power.

Furthermore, from a physical design perspective, the power grid in top-level needs to be aligned with the power grid in block-level. This needs proper selection of pitch, width and spacing between metals in the power grid. Due to these constraints, there is IR drop in each block and so, power analysis (static + dynamic) needs to be clean at these blocks for signoff - read more.

4. Dynamic Voltage & Frequency Scaling (DVFS)

This technique uses a separate control unit to control power to different regions in a design so that voltage levels are adjusted dynamically or adaptively based on functionality. Again there is a tradeoff in area for the power control circuitry. Apart from adjusting voltage levels, frequency can also be dynamically adjusted where performance is not a priority, thereby saving some power.

ESD Cells

Due to shrinking feature sizes and increasing metal layer stack, Electro-Static Discharge (ESD) has become another major concern for low-power VLSI designs. Due to static electricity that could be produced in any uncontrollable exposed environment such as Human Body Interaction (HBM), Machine Handling (MH) or from internal build-up of charge leaving through the package (CDM or Charged Device Model), chip shouldn’t get exposed and affected due to these factors.

ESD or Electro-Static Discharge cells are clamp circuits that are placed at appropriate locations inside the chip to provide a low impedance discharge path for the ESD current, handle large transient current and clamp the signal voltage at a level that avoids dielectic breakdown. In modern chip design, ESD cells are mandatory to avoid functional failure or burn out of the chip.

Apache RedHawk is the industry standard tool to comprehensively analyse, plan and verify ESD at full chip-level that ensures connectivity between any two pins meets design guidelines. Apache’s PathFinder is capable of performing ESD connectivity analysis for HBM, MM and CDM ESD events and predicts the current density in all metal wires and vias - read more.


In case if you found something useful to add to this article or you found a bug in the code or would like to improve some points mentioned, feel free to write it down in the comments. Hope you found something useful here.