Physical Design - Terminologies

PD Concepts | 17 June 2018

In Physical Design (PD), there are so many terminologies involved. It could be daunting for a fresher to get acquainted with these terms at the beginning of his career. So, I thought of making a page with terminologies and its description. It might be helpful for a beginner or an experienced professional to quickly refer something related to PD.

I will be regularly updating this page if I found some new terminology along with its description. Make sure you bookmark it. 😉


  • Aspect Ratio

    It is the ratio between height and width of the core or a block. Routing resources, congestion, placement of standard cells, timing, clock-tree, placement of IO pads and packaging depends on the aspect ratio of the core or a block.

$$ aspect\;ratio = \frac{height\;of\;the\;core}{width\;of\;the\;core} $$
  • Cell Orientation

    Every instance in a design such as a block, a macro, an IO pad or a standard cell have orientation associated with them. Orientation is defined as the rotation and/or mirroring of that instance about x or y axis to make connections meaningful and easier. Different types of cell orientations are R0, MX, MY, R90, R180, R270, MX90, MY90.

    • R0 - No rotation.
    • MX - Mirror through x-axis.
    • MY - Mirror through y-axis.
    • R90 - Rotate 90 degrees counter-clockwise.
    • R180 - Rotate 180 degrees counter-clockwise.
    • R270 - Rotate 270 degrees counter-clockwise.
    • MX90 - Mirror through x-axis and rotate 90 degrees counter-clockwise.
    • MY90 - Mirror through y-axis and rotate 90 degrees counter-clockwise.
  • Core Boundary

    It is the area or region within which standard cells and macros are placed in the design. From top-level of a design, core boundary will be rectangular or square shaped. From block-level of a design, core boundary may have rectangular or rectilinear shape.

  • Core Utilization

    It defines the total area occupied by the standard cells and macros in the block or top-level design. Typically, 70-80% utilization is taken into account for blocks as timing optimization involves placement of buffers or inverters which requires area.

$$ core\;utilization = \frac{standard\;cell\;area\;\;+\;macro\;cells\;area}{total\;core\;area} $$
  • Flylines

    These are virtual lines that shows logical connections from an instance (block or macro or cell or IO pad). Using flylines, one can understand different connections from a block or a macro or a cell or an IO pad with which floorplanning could be done easily.

  • Halo

    It is the area around the boundary of a block or a macro or a standard cell within which no other block or standard cell or macro is placed. If the blocks or standard cells or macros are moved, halos for those instances move along with it. It is also called as the keepout region. Halos of two adjacent instances can be overlapped.

  • Instance

    A single occurance or a single object of a standard cell type or a macro or a block defined with a unique instance name. Ex: a 2-input AND gate could be instantiated as CELL_AND_1 and a usb 2.0 macro could be instantiated as USB_2_0_1.

  • Macro

    A Macro is an Intellectual Property (IP) in a design that is owned by a company. These are reusable logic blocks used in a design without the necessity of building them from scratch. Two types of macro are Soft Macro and Hard Macro.

    • Soft Macro is not specific to any technology node. Due to this, soft macros are unpredictable in terms of timing, area and power. But soft macros are more flexible in terms of reconfigurability and can be modified at the RTL level.
    • Hard Macro is what we call as a Block in PD. It is designed specific to a technology node to meet timing, area and power.
  • Manufacturing Grid

    The smallest resolution of the technology node is called as the Manufacturing Grid. Any geometry (or shape) created in the design must be snapped (or aligned) with this grid to avoid DRC errors.

  • Net

    A logical connection between two or more pins of different instances. Some of the different types of net in a design are single fanout net, multi-fanout net, power net, ground net, signal net, clock net etc.

  • Physical Cells

    These cells do not have any logical functionality in the design. Some of the standard physical cells are tap cells, tie cells, endcap cells, decap cells, filler cells, spare cells.

  • Pin

    A pin is an IO terminal that is present in blocks or hard-macros or standard-cells of a design. Ex: For a 2-input AND gate, CELL_AND_1/a, CELL_AND_1/b are the input pins and CELL_AND_1/z is the output pin.

  • Placement Blockage

    It is the area defined by the designer for the PnR tool to avoid placing, legalizing or overlapping standard cells in that particular area. If a block or standard cell or macro or IO pad is moved, placement blockages does not move along with it.

    • Hard placement blockage means that the tool must not place, legalize or overlap any standard cell (including buffers and inverters) in the mentioned blockage area.
    • Non-buffer blockage means that the tool can place, legalize or overlap any buffer or inverter in the mentioned blockage area except other standard cells in the design.
    • Partial blockage means that the designer can adjust the percentage of blockage inside the blockage area and the tool should honor it. By default, 100% placement is blocked inside the blockage area.
  • Placement Grid

    Placement grid is a multiple of the manufacturing grid in which all the standard cells are placed. Based on the placement grid, rows are formed and standard cells are placed.

  • Port

    A port is an IO (Input/Output) terminal that is present in blocks or hard-macros of a design. From top-level, ports are pins in hard-macros or blocks. But from block-level, pins talking to top-level are celled as ports. Direction of ports can be input, output or in-out.

  • Power Domain

    It is the collection of instances or blocks that share the same supply voltage in a design. Each power domain has a separate library associated with it.

  • Routing Blockage

    It is the area defined by the designer for the PnR tool to block routing resources in single or multiple metal layers at a particular area. Routing blockages can be created and removed at any point in the design based on the requirements. It is possible to create routing blockages over a block or an instance using it’s cell type or instance name without the area numbers.

  • Row

    Standard cell row is the area defined for placing standard cells in the design. Every standard cell in the design sits on the standard cell row. The row height is based on the standard cell height used in the design. Different types of rows are possible in a design based on sites or heights of standard cells used.

  • Track

    Track is a virtual line (guideline) for the PnR tool in which routing of metal wires happen in the design. For each metal layer in the design, tracks are defined for preferred and non-preferred direction with specific pitch and offset. The PnR tool routes the metal wires by assuming the track at the center of metal piece.

  • Voltage Island

    It is a dedicated area in the design which has its own row, site, cells and power structure defined for better power consumption. Level-shifters are used to convert from one voltage level to another.

  • Wire

    A physically realized connection of a net which is routed by the router by having the center of metal piece in the track (on-track) using same or different metal layers and vias.


  • Cell Legalization

    It means all standard cells must be placed on the standard cell rows (in placement grid) without any off-grid violations and overlaps. Only if all cells are legalized, the PnR tool will proceed with routing.

  • Cell Padding

    It is a variable assigned to all standard cells or specific standard cell instances that belong to a cell-type in the design. Using this variable, the cell instances will have a padding associated with it around which other cells or blocks wont be placed. It’s like a breathing-space for a cell which is used to avoid congestion.

  • Driver

    Any pin (or output pin) that drives one or multiple pins is called as a driver pin and it’s corresponding instance is called as the driver. There can always be only one driver pin in a design.

  • Fanin

    The maximum number of inputs that a standard cell (or a logic gate) can accept is termed as the fanin of that standard cell.

  • Fanout

    The maximum number of inputs (loads) that the output of a single standard cell (driver) can drive is termed as the fanout of that standard cell.

  • Load

    Any pin (or input pin) that acts as a load for a driver pin is called as a load pin. There can be one or more load pins for a single driver pin, hence the term multi-fanout.

  • Placement Density

    It is the amount of area utilized for placing cells (except filler cells) in the design. There is a golden equation that this placement density should be lesser than or equal to 70% so that the remaining 30% can be used for routing resources.

  • Standard Cells

    Any complex chip is built using basic building blocks in digital design such as and, or, not, nor, nand, flipflop, buffer etc. Based on a technology node, these building blocks (called standard cells) are predesigned (i.e will have logical, symbol, abstract, layout and schematic views plus timing information for different scenarios) and given to the IC designer. Standard cells have fixed height and variable width. Height of these cells are same as the height of a standard cell row. In some cases, there might be double-height or triple-height cells that occupies two or three rows respectively.


  • Congestion

    If the number of available routing tracks for routing in a particular area is lesser than the number of required routing tracks, then that particular area is said to be congested. Congestion creates shorts and DRCs which makes functionality fail in a design.

  • Detailed Routing

    Detail routing determines the exact physical routing for all the logical nets in the design with the help of track assignment, wires and vias insertion at different metal layers. Real picture of congestion, metal DRCs and crosstalk issues are known only after detail routing the design.

  • Global Routing

    Global routing partitions the entire design into tiles or global routing cells or g-cells and then, the paths for various nets are computed. Global routing doesn’t necessarily assign specific tracks to each net, but assigns each net to specific g-cells. Congestion can be estimated earlier in the design using Global routing before starting detail routing.

  • Metal Layers

    Based on technology node, there are different metal layers involved for routing. Each metal layer is designated with a name say M1 or M3 and each metal layer has preferred and non-preferred directions with well-defined width, pitch, offset and tracks. Ex: M1 can have preferred direction as vertical and non-preferred direction as horizontal, while M4 can have preferred direction as horizontal and non-preferred direction as vertical.

  • NDR

    Non-Default Rule is a routing rule applied for a single net or a group of nets that is not default. Default routing rule have defined width and spacing for each metal layer and via. Using Non-Default Rules, one can create an NDR rule with double or triple the width with double or triple the spacing. Ex: 1W2S means single width and twice the default spacing. NDRs are used for clock nets and critical nets (high-frequency nets) in a design to avoid Signal Integrity (SI) issues such as crosstalk and noise.

  • Shorts

    When two or more wires or vias of different nets in the same metal layer cross each other, then it is termed as a short. Shorts are the number one concern after detail routing a block. These overlapping wire segments must be corrected for proper functioning of the design.

  • VIA

    Vertical Interconnect Access (VIA) is the small vertical path (or opening) in an insulating oxide layer (cut-layer) that allows a conductive path (or connection) between different metal layers. Some types of VIA are single VIA, stacked VIA, VIA array etc.

Power Distribution

  • PMIC

    PMIC or Power Management Integrated Circuit takes care of all possible supported external supplies and defines the power sequence for the board. It supplies power to different components inside the board. Also, it protects the board from unsupported overvoltage and undervoltage. It is usually software-controllable (often as an I2C device). Different voltage values such as VDD_1, VDD_2, VDD_3 etc., inside a chip are obtained using a PMIC.

  • Gridcheck

    Gridcheck is a verification process that is performed to check for opens and shorts in the power distribution grid of a design. For a design to function properly, it must be free from opens and shorts. Before analyzing a design for static and dynamic IR drop, it must be free from opens and shorts (i.e. zero opens and zero shorts).

  • Static IR Drop

    As the name suggests, even when the chip is off or quiescent (static), there exists some amount of power dissipation due to transistor’s leakage characteristics giving rise to leakage power. This is due to the characteristic of CMOS transistors itself, which is a function of power supply voltage \( V_{DD} \), threshold voltage \( V_{th} \) and transistor’s dimension (width \(W \) and length \( L \)). Static IR drop analysis is a vectorless IR drop analysis with average current cycles. It is typically used for Electro-Migration (EM) analysis where current limit is checked for wires.

  • Dynamic IR Drop

    As the name suggests, dynamic power dissipation occurs when the transistors are switching from one logic state to another. There are two types of dynamic power dissipation in CMOS circuits namely switching power and short-circuit power. Dynamic IR drop analysis is a vectorless or VCD based IR drop analysis with worst-case switching currents. It is typically used to check voltage drop limit for switching instances.

  • ESD Cell

    ESD or Electro-Static Discharge cells are clamp circuits that are placed at appropriate locations in the chip to provide a low impedance discharge path for the Electro-Static Discharge and clamp the signal voltage at a level that avoids dielectic breakdown. As technology node decreases in feature size, ESD cells are mandatory to avoid functional failure or burn out of the chip.

Physical Verification

  • Antenna

    Antenna violation, commonly referred as the plasma induced gate oxide damage, occurs during manufacturing stage of a chip. It is a result of charge accumulation on metals and discharge to a transistor’s gate through gate oxide which ultimately damages the gate.

  • DRC

    Design Rule Checks are performed at the physical design stage to verify if the designed layout meets the design rules so that the design can be manufactured properly without any issues. These design rules are specific to a technology node and are provided to the designer by the foundry. Base and Metal are checked and verified completely with zero DRC error before tapeout. DRC include physical layout checks such as metal width, metal pitch, metal spacing, via spacing, via type, base (well connectivity).

  • LVS

    Layout vs Schematic is another physical verification check that is performed at the physical design stage. This is to ensure that the designed layout is functionally the same as the schematic netlist so that there isn’t any deviation in functionality of the design. There must be zero opens and shorts without any DRC errors. Some other LVS errors are parameter mismatches and unbound pins.

  • ERC

    Electrical Rule Check is a physical verification check that reports any electrical connection that is potentially dangerous. It checks the design for accurate power and ground connections. Transistors with gate unconnected (floating gate), wrong transistor-level connections (such as shorted drain and source, connecting high voltage to thin gates), floating nets, floating pins, floating wells, antenna errors are some of the checks reported here.

In case if you found something useful to add to this article or you found a bug in the code or would like to improve some points mentioned, feel free to write it down in the comments. Hope you found something useful here.