When I was a kid, I used to spend time with playstation and computers. At that time, I always wondered how those tiny components inside rectangular black boxes entertain me by making me play cool games and watch movies. When I grew up, I realized its the combination of logic design and physical design that makes an Integrated Circuit that is sitting inside the device you currently hold in your hand.
In this blog post, we will learn the basics of VLSI physical design or VLSI backend design that is used to create modern ICs that power up numerous electronic applications.
What is VLSI Physical Design?
The final output of a frontend design or circuit design or logic design is a netlist. Netlist contains the logical functionality of your chip. This netlist could be viewed as a plethora of instances with interconnections between them based on the functionality you wish to implement.
This connectivity information in a netlist is a layer of abstraction of your hardware which must be converted to a physically realizable format (having geometric shapes) that is manufacturable.
The process of converting a gate-level netlist into a physically realizable format (GDSII) which finally becomes the hardware is called Physical Design.
Actually, Physical Design contains a lot more steps to be done than the above simplified definition. Figure 1 shows the conversion of a simple transistor level circuit to a physically realizable layout.
In VLSI, Physical Design is the only domain where you can see circuits in a Graphical User Interface (GUI) with geometric shapes and colors as shown in Figure 2. It is an excellent career choice for engineering minds with an artistic background.
Physical Design involves dedicated flows and methodologies for each step in the design process with the help of EDA tools and scripts.
A design is poor if it is not verified and validated 100% before manufacturing. Hence, Physical Design involves robust verification flows to verify and validate the design in terms of timing, power and area.
Why VLSI Physical Design Flow?
Physical design is all about placing instances defined in the netlist and connecting them by routing through metal layer stack to satisfy design specifications such as timing, power and area. Current IC designs have multi-million instances that are interconnected with several stack of metal layers that connect these instances. Manually performing each step in the design process is not feasible, takes huge amount of time and is error prone.
The complexity in designing a multi-million instance based IC is huge and hence we need dedicated automation flows that complete specific tasks needed to be performed at each step in the design which reduces design time and errors. These flows require knowledge and understanding of EDA tools and scripting languages such as Tcl, Perl or Python.
In addition to complexity, as time to market for chips is decreasing, reuse of IP (Intellectual Property) blocks is highly preferred in each design.
VLSI Physical Design Flow
Typical VLSI Physical Design (PD) flow is shown in Figure 1. This is a standard flow that is followed in modern IC design. Each step in the PD flow has sub flows or further steps that are needed to be performed.
Major steps involved in Physical Design are
- Power Planning
- Clock Tree Synthesis (CTS)
Major verification steps involved in Physical Design are
- Static Timing Analysis (STA)
- Power Distribution Network Analysis (PDN)
- Physical Verification (PV)
Commonly used EDA tools for Floorplanning and Place and Route are
- Cadence Innovus, Cadence Encounter
- Synopsys IC Compiler II
Commonly used EDA tools for STA, PDN and PV are
- Synopsys PrimeTime
- Apache RedHawk
- Mentor Graphics Calibre
Related Terminologies: [Floorplanning]
Goal: Calculate the size of blocks, figure out the position of blocks and do power planning. Keep highly connected blocks physically close to each other.
In today’s IC design, because of huge design complexity, hierarchical design approach is followed. What this means is, the entire chip is divided into partitions or sub-blocks that are interconnected at a TOP_LEVEL module.
This TOP_LEVEL module contains hard blocks and soft blocks with or without glue logic.
- hard blocks are those sub-blocks whose shapes cannot be changed. These blocks are mostly IPs or macros that are already designed and validated for that particular technology node.
- soft blocks are those sub-blocks whose shapes can be changed to meet predefined cost metrics such as chip area, wirelength and wire congestion. These are the blocks that are needed to be designed and validated for chip-level convergence.
During floorplanning, one must ensure proper shapes for the soft blocks until convergence is reached in terms of cost metrics, timing and power.
Due to design complexity and runtime of EDA tools, each soft block is created using the same design steps such as floorplanning, placement and routing and then integrated at the TOP_LEVEL module.
PD is all about tradeoffs between area and speed. Thus, floorplanning is a highly iterative process which takes into account the hard blocks and soft blocks used, memories, IO pads and their placement in the design, routing possibilities between different blocks and inside the blocks, power grid structure for each block and cell in the design, and also the aspect ratio and IO structure of the entire design.
Related Terminologies: [Partitioning]
Goal: Divide the entire chip into smaller blocks so that design convergence is achieved faster and time to market is reduced.
Dividing the entire design into smaller sub-designs (blocks) makes design convergence easier. This is because, the runtime of EDA tools for a single block will take lesser time for each step in the PD flow when compared to entire design.
Partitioning is also done to separate blocks based on functionality as well as to make placement and routing easier. All these sub-blocks are interconnected at the TOP_LEVEL module.
Related Terminologies: [Power Distribution]
Goal: Decide on power dissipation number and construct power distribution network accordingly to power up blocks, IO pads, macros and standard cells.
VDD and VSS that you see in the transistor level circuit in Figure 1 needs to be supplied to every transistor in a multi-million transistor design. Thus, power from a single battery source must be delivered to each cell in the design. To accomplish this, power planning is done.
During floorplanning, power planning is a step that is done to construct the power grid network to supply power to all blocks, macros and standard cells equally.
Typically, there are two types of power distribution in a chip namely Wire Bonding and Flip-Chip (read more). Using any one of these two power distribution strategies, we usually form power rings, stripes and rails through out the design.
- Rings - Supplies VDD and VSS around the chip.
- Stripes - Supplies VDD and VSS across/throughout the chip.
- Rails - Supplies VDD and VSS to the standard cells in the design.
Main steps to be taken care during power planning are
- Decision on width, pitch and offset of power stripes for each metal layer.
- Block power hook up at TOP_LEVEL.
- IO power hook up at TOP_LEVEL.
- Standard cells power hook up inside block as well as TOP_LEVEL.
- Shorts and Opens needed to be checked and fixed.
Related Terminologies: [Placement]
Goal: Place all the standard cells in the design to minimize total area, reduce interconnect cost and
After floorplanning the design, for each block, standard cells are placed inside the block. These standard cells are the cells that contain the necessary logic functionality. Inside the standard cells, you could find the individual transistors that make up the logic functionality. Ex: AND gate, OR gate, 2x1 multiplexer etc.
In a multi-million instances design, placing these cells manually is not feasible. Hence, EDA tool place these cells in the standard cell rows to optimize timing. This is achieved with the help of virtual route.
Virtual route is a rough estimate for the EDA tool to measure the shortest manhattan distance from one pin to another. Based on this distance, timing is calculated roughly and these cells are placed accordingly.
A good placement reduces the delay of interconnect wires, has shorter interconnect wire length and has lesser congestion hotspots. One key thing performed during placement is legalization which means placing standard cells at appropriate locations without any placement constraint violation.
Clock Tree Synthesis
Related Terminologies: [Clock Tree Synthesis]
Goal: Minimize skew, latency and insertion delay for clock signals reaching all the sequential elements in the design.
Clock is an important component in digital design as sequential circuits such as flipflops and registers require clock signal to function properly. Before clock tree synthesis, the clock is considered as ideal i.e. right from the source it travels to all the pins without any delay. But after CTS, the clock is propagated which means there is considerable amount of delay involved between the clock signal entering one flipflop and another flipflop which is defined as clock skew.
The goal of clock tree synthesis is to reduce this clock skew, balance it and minimize insertion delay. This is done with the help of constructing a clock tree using clock tree inverters to maintain exact duty cycle (transition) and clock tree buffers to balance the skew and latency involved.
Additionally, these clock tree inverters and buffers should be added carefully with area and power constraints in mind.
Related Terminologies: [Routing]
Goal: Physically connect all the interconnects (nets) in the design with constraints such as DRC, wire length, timing, noise and crosstalk to be taken care.
After placing all the standard cells in the design, interconnects (nets) must be routed physically. Routing is typically done in two steps
- Global Routing - Generate a rough route (routing region, track assignment) for each net in the design without specifying the actual layout of wires (loosely routed).
- Detail Routing - Generate actual geometry layout for each net in the design using different metal layers.
Main steps to be taken care during routing are
- Wire length must be minimized.
- Congestion must be reduced.
- Noise & Crosstalk must be reduced using shielding.
- DRC rules must be honored while detail routing.
- Shorts must be reduced.
Static Timing Analysis
Related Terminologies: [Static Timing Analysis]
Goal: Validate the design with respect to timing and verify whether the design could operate at the specified clock frequency without any timing violations such as setup and hold.
Once the design is placed and routed, it is validated for timing. STA involves checking whether the design meets the specified clock frequency and is free of timing violations such as setup, hold, maximum transition, maximum capacitance etc.,
STA depends on parasitic extraction which is a process of extracting the R (resistance) and C (capacitance) of the interconnect metal traces in the design. These parasitics cause delay that is further added by the gate delay, resulting in timing degradation.
Related Terminologies: [Power Verification]
Goal: Validate the design with respect to power and verify whether the design meets static and dynamic IR drop thresholds, and free from electromagnetic effects.
Similar to timing validation, power analysis and debugging is done to ensure that the design is free from power related issues such as static IR drop, dynamic IR drop and electromagnetic issues.
Only if the design meets power numbers specified in the design specifications, it can last longer. Hence, power is a primary concern for chip designers due to decreasing technology node and increasing metal layer stack.
You can read more about low power design in the below links.
In case if you found something useful to add to this article or you found a bug in the code or would like to improve some points mentioned, feel free to write it down in the comments. Hope you found something useful here.